Multi-chip package semiconductor device and method of detecting a failure thereof

ABSTRACT

A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.

PRIORITY STATEMENT

This U.S. non-provisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2005-109443, filed on Nov. 16, 2005in the Korean Intellectual Property Office (KIPO), the entire contentsof which are incorporated herein by reference.

BACKGROUND

1. Field

Example embodiments relate to a multi-chip package (MCP) semiconductordevice and a method of detecting a failure thereof, for example, anapparatus and a method of detecting a failure of respective chips in themulti-chip package semiconductor device.

2. Description of the Related Art

The demand for electronic devices to be lighter, thinner, and overallsmaller-sized electronic devices may be rapidly increasing. Therefore, asemiconductor chip package may need to have a high integration level andbe smaller in size. Accordingly, the semiconductor chip package may beimplemented in a form of a multi-chip package where at least two chipsmay be laminated.

The at least two chips may be included in the multi-chip package so thatthe electronic devices, for example mobile phones, may be manufacturedto be thinner and smaller size and through a simplified manufacturingprocess. The at least two chips in the multi-chip package may be of thesame kind, but the at least two chips of may each be of a differentkind. However, if chips of different kinds are combined in a multi-chippackage, external connection terminals may be shared by the chips, andthus it is may be difficult to test the respective chips in themulti-chip package for failure using an external tester.

Conventional techniques for determining a disconnection of a bondingwire between internal chips and an external terminal may not detect adefect in current flowing through the logic blocks of the internalchips. For example, a defect in current flowing through the logic blocksmay not be determined by simply identifying the connection between theinternal chips and the external terminal through the wire.

In addition, a technique for individually testing the respective chipsunder external control may be required to more precisely perform a testfor detecting failure in the multi-chip package semiconductor devicewithout damaging the package.

SUMMARY

Example embodiments may provide a multi-chip package semiconductordevice and a method that may detect a failure in respectivesemiconductor chips of a multi-chip package.

Example embodiments may provide a semiconductor chip that may be capableof detecting a failure of the chip individually if the semiconductorchip is configured within a multi-chip package.

In an example embodiment, a semiconductor device may include at leastone power supply pad for receiving an external power voltage, at leastone input/output pad, an internal function block that may be configuredto operate based on a power voltage and may be configured to at leastone of receive and transmit a signal through the input/output pad, and amode set circuit that may be configured to enable or disable the powervoltage based on a mode set signal in an individual chip test mode.

According to an example embodiment, an internal power supply circuit maybe configured to generate an internal power voltage based on theexternal power voltage provided through the at least one power supplypad, wherein the internal function block may be configured to operatebased on the internal power voltage, and the mode set circuit may beconfigured to enable or disable the internal power supply circuit.

According to an example embodiment, a switching unit may be coupledbetween the internal function block and a first power supply pad of theat least one power supply pad, and the internal function block may beconfigured to be operated based on the external power voltage, and themode set circuit may be configured to turn on or turn off the switchingunit.

According to an example embodiment, the first power supply pad maycorrespond to a high level power supply pad, and the switching unit maybe a PMOS transistor.

According to an example embodiment, the first power supply pad maycorrespond to a low level power supply pad, and the switching unit maybe an NMOS transistor.

According to an example embodiment, a multi-chip package semiconductordevice may include a plurality of semiconductor chips; a power supplyterminal that may be configured to commonly couple the power supply padsof the plurality of semiconductor chips to an external device; and asignal terminal that may be configured to commonly couple theinput/output pads of the plurality of semiconductor chips to theexternal device.

In an example embodiment, a method of detecting a failure insemiconductor chips of a multi-chip package semiconductor device mayinclude commonly providing power to the semiconductor chips of themulti-chip package semiconductor device through a power supply terminal;setting one of the semiconductor chips to a disabled state and the restof the semiconductor chips to a enabled state based on a test mode setsignal; measuring a current running through the power supply terminalthat may be commonly coupled to the semiconductor chips; and determininga failure of the disabled semiconductor chip by comparing the measuredcurrent and a normal current corresponding to a normal operation state.

According to an example embodiment, setting one of the semiconductorchips to a disabled state may include preventing an internal powervoltage from being provided to an internal function block of thedisabled semiconductor chip; and allowing the internal power voltage tobe provided to the internal function block of the enabled semiconductorchips.

According to an example embodiment, the semiconductor chips may besequentially set to a disabled state, and measuring current flowingthrough the power supply terminal and determining failure of theindividually disabled semiconductor chip for the rest of thesemiconductor chips may be repeated for each disabled semiconductorchip.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be described with reference to the accompanyingdrawings.

FIG. 1 is a block diagram of a multi-chip package semiconductor deviceaccording to an example embodiment.

FIG. 2 is a flow chart of a method of detecting a failure of amulti-chip package semiconductor device according to an exampleembodiment.

FIG. 3 is a block diagram of a multi-chip package semiconductor deviceaccording to an example embodiment.

FIG. 4 is a block diagram of a multi-chip package semiconductor deviceaccording to an example embodiment.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments now will be described more fully with reference tothe accompanying drawings. The example embodiments may, however, beembodied in many different forms and should not be construed as limitedto the example embodiments set forth herein. Rather, these exampleembodiments are provided so that this disclosure will be thorough andcomplete. Like reference numerals refer to like elements throughout thisapplication.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between,” “adjacent” versus “directlyadjacent,” etc.).

The terminology used herein is for the purpose of describing particularexample embodiments and is not intended to be limiting. As used herein,the singular forms “a,” “an” and “the” are intended to include theplural forms as well, unless the context clearly indicates otherwise. Itwill be further understood that the terms “comprises,” “comprising,”“includes” and/or “including,” when used herein, specify the presence ofstated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a block diagram of a multi-chip package (MCP) semiconductordevice according to an example embodiment.

Referring to FIG. 1, an MCP semiconductor device 100 may include powersupply terminals 102 and 104, a signal terminal 106, and/orsemiconductor chips 110 and 120 that may be sealed by resin to constructa single package.

The semiconductor chip 110 may include pads 111 and 112 of power supplyvoltages VCC and VSS, an internal power supply circuit 113, an internalfunction block 114, a mode set circuit 115 and/or an input/output pad116.

The semiconductor chip 120 may include pads 121 and 122 of the powersupply voltages VCC and VSS, an internal power supply circuit 123, aninternal function block 124, a mode set circuit 125 and/or aninput/output pad 126.

The power supply pads 111 and 121 may be commonly coupled to the powersupply terminal 102 to receive a higher level power voltage EVCC. Thepower supply pads 112 and 122 may be commonly coupled to the powersupply terminal 104 to receive a lower level power voltage GND. Theinput/output pads 116 and 126 may be commonly coupled to the signalterminal 106.

The internal power supply circuits 113 and 123 may be coupled betweenthe power supply pads 111 and 112 and the power supply pads 121 and 122,respectively, to generate an internal power voltage IVC based on theexternal power voltage EVCC. The internal power supply circuits 113 and123 may be enabled or disabled in response to a mode set signal that maybe output from the mode set circuits 115 and 125. If the internal powersupply circuits 113 and 123 are enabled, the internal power voltage IVCmay be provided to the internal function block 114 and 124. If theinternal power supply circuits 113 and 123 are disabled, the internalpower voltage IVC may not be provided to the internal function block 114and 124.

The internal function blocks 114 and 124 may perform given functionsbased on the internal power voltage IVC and may receive or transfer asignal through the input/output pads 116 and 126. In addition, theinternal function blocks 114 and 124 may receive a mode set signal thatmay be provided from the outside and may transfer the mode set signal tothe mode set circuit 115 and 125. For example, an internal functionblock may be a memory function block or a logic function block, but isnot limited thereto.

Each of the mode set circuits 115 and 125 may include a power-up circuitand a latch circuit. In an initial power-on stage, the latch circuit ofthe mode set circuits may be latched to an enabled state by the power-upcircuit. The latch circuit may transition to a disabled state or anenabled state in response to the mode set signal. The mode set circuits115 and 125 may receive the power voltages VCC and VSS, respectively,and may continue to operate even if the internal power supply circuits113 and 123, respectively, are disabled. For example, the mode setcircuits 115 and 125 may have configuration similar to that of a modeset register(MSR) in a memory chip, for example, a synchronous DRAM(SDRAM).

If the power is provided in an initial driving state, the mode setsignal input to the mode set circuits 115 and 125 may be at logic “1” sothe output of the mode set circuits 115 and 125 may be at logic “1.”Accordingly, the internal power supply circuits 113 and 123 may beenabled to provide the internal power voltage IVC to the internalfunction blocks 114 and 124.

If the mode set signal is set to logic “0” by a particular addresscombination, the output of the mode set circuits 115 and 125 maytransition to logic “0.” Accordingly, the internal power supply circuits113 and 123 may be disabled so that the internal power voltage IVC maynot be provided to the internal function blocks 114 and 124.

Thus, to detect a current failure in an individual chip of the MCPsemiconductor device 100, an amperemeter 130 may be disposed between thepower supply terminal EVCC 102 and a ground GND 104 to measure thecurrent flowing.

FIG. 2 is a flow chart of a method of detecting a failure of amulti-chip package (MCP) semiconductor device according to an exampleembodiment. In an example embodiment, an MCP semiconductor device may becoupled to a tester (not shown).

Referring to FIGS. 1 and 2, a method of detecting the failure of an MCPsemiconductor device according to an example embodiment, may includeproviding power to the MCP semiconductor device., and initializing avariable “i” to “N” (operation S200). For example, “N” may be the numberof chips in the MCP semiconductor device.

It may be determined whether or not the variable “i” has a value of “0”(operation S202). If the variable “i” has a value of “0” (operationS202: YES), testing “N” chips of the MCP semiconductor device may bedetermined as being completed, so that a testing operation may beterminated. If the variable “i” does not have a value of “0” (operationS202: NO), a mode setting operation may be performed.

In the mode setting operation, the chips may be initially set in anenabled state. A chip corresponding to the variable “i” (i-th chip) maybe disabled, and the rest of chips may be maintained in the enabledstate (operation S204). For example, the internal power voltage IVC maynot be provided to the internal function block of the i-th chip that maybe disabled by the internal power supply circuit, and the internal powersupply circuits of the rest of chips may be maintained at an enabledstate so that the internal power voltage IVC may be provided to theinternal function block of the rest of chips.

In an individual chip test mode, all the chips may be maintained in astand-by mode and the current flowing through the power supply terminalmay be measured by the amperemeter (operation S206). If the i-th chip isnormal, a normal current that may be the sum of stand-by currents of thechips except the i-th chip may be measured by the amperemeter. If thei-th chip is not normal (e.g., when failure occurs in the i-th chip),the internal power circuit of the i-th chip may operate abnormally toprovide power to the internal function block even though the internalpower circuit of the i-th chip may be disabled by the mode settingoperation. Therefore, the stand-by current may also be generated by thei-th chip if the i-th chip has a defect. For example, the currentmeasured by the amperemeter may be the sum of the stand-by currents ofall the chips in the MCP semiconductor device, and thereby may begreater than the normal current.

A current value that may be measured in operation S206 may be comparedwith a normal current value (operation S208). If the measured currentvalue is equal to the normal current value (operation S208: YES), thei-th chip may be determined as being normal (operation S210). If themeasured current value is not equal to the normal current value(operation S208: NO), the i-th chip may be determined as being defective(operation S212).

If the i-th chip is tested, the variable “i” may be decreased by “1”(operation S214) so as to sequentially test the next chip. The aboveprocedure may be repeated to test the (i−1)-th chip.

Therefore, by sequentially decreasing the variable “i,” all of the chipsmay be tested and defective chips among a plurality of those may bedetermined by the above method.

FIGS. 3 and 4 are block diagrams of a multi-chip package semiconductordevice according to example embodiments.

The same or like reference numerals are used to refer to the same orlike elements as those described in the example embodiment in FIG. 1 andany repeated explanation will be omitted. In the MCP semiconductordevices of FIGS. 3 and 4, the internal power supply circuit may not beincluded.

Referring to FIG. 3, an MCP semiconductor device may include PMOStransistors 117 and 127 that may be disposed between the power supplypads 111 and 121 and the internal function blocks 114 and 124,respectively, to switch on and off the connection from the power supplyvoltage VCC to the function blocks 114 and 124. Control signals that maybe output from the mode set circuits 115 and 125 may be applied to gatesof the PMOS transistors 117 and 127, respectively. Each of the PMOStransistors 117 and 127 may be turned on in response to thecorresponding control signal having a logic low level and may be turnedoff in response to the corresponding control signal having a logic highlevel. For example, if chip 110 is tested, the PMOS transistor 117 ofthe chip 110 may be turned off and the PMOS transistor 127 of the chip120 may be turned on.

Referring to FIG. 4, an MCP semiconductor device may include NMOStransistors 118 and 128 that may be disposed between the power supplypads 112 and 122 and the internal function blocks 114 and 124,respectively, to switch on and off the connection from the power supplyvoltage VSS to the function blocks 114 and 124. Control signals that maybe output from the mode set circuits 115 and 125 may be applied to gatesof the NMOS transistors 118 and 128, respectively. Each of the NMOStransistors 118 and 128 may be turned on in response to thecorresponding control signal having a logic high level and may be turnedoff in response to the corresponding control signal having a logic lowlevel. For example, if chip 110 is tested, the NMOS transistor 118 ofthe chip 110 may be turned off and the NMOS transistor 128 of the chip120 may be turned on.

Thus, the chips 110 and 120 may be independently enabled or disabled bycontrolling the switching transistors, which may be disposed in powersupplying paths to the internal function blocks and which may operate inresponse to the control signals from the mode set circuits 115 and 125.The mode set circuits 115 and 125 may output the control signals inresponse to the mode set signal.

According to an example embodiment, the internal power supply circuitsof the semiconductor chips may be independently enabled or disabled byusing an externally provided mode set signal, so that the chips of themulti-chip package semiconductor device may be tested.

Although example embodiments have been described above, it is to beunderstood that the appended claims are not to be limited by particulardetails set forth in the above description as many apparent variationsthereof are possible without departing from the spirit or scope thereofas hereinafter claimed.

1. A semiconductor chip comprising: at least one power supply pad forreceiving an external power voltage; at least one input/output pad; aninternal function block configured to operate based on a power voltageand configured to at least one of receive and transmit a signal throughthe at least one input/output pad; and a mode set circuit configured toenable or disable the power voltage based on a mode set signal in anindividual chip test mode.
 2. The semiconductor chip of claim 1, furthercomprising an internal power supply circuit configured to generate aninternal power voltage based on the external power voltage providedthrough the at least one power supply pad, wherein the internal functionblock is configured to operate based on the internal power voltage andthe mode set circuit is configured to enable or disable the internalpower supply circuit.
 3. A multi-chip package semiconductor devicecomprising: a plurality of the semiconductor chips of claim 2; a powersupply terminal configured to commonly couple the power supply pads ofthe plurality of semiconductor chips to an external device; and a signalterminal configured to commonly couple the input/output pads of theplurality of semiconductor chips to the external device.
 4. Thesemiconductor chip of claim 1, further comprising a switching unitcoupled between the internal function block and a first power supply padof the at least one power supply pad, wherein the internal functionblock is configured to operate based on the external power voltage andthe mode set circuit is configured to turn on or turn off the switchingunit.
 5. The semiconductor chip of claim 4, wherein the first powersupply pad corresponds to a higher level power supply pad, and theswitching unit is a PMOS transistor.
 6. The semiconductor chip of claim4, wherein the first power supply pad corresponds to a lower level powersupply pad and the switching unit is an NMOS transistor.
 7. A multi-chippackage semiconductor device, comprising: a plurality of thesemiconductor chips chip of claim 4; a power supply terminal configuredto commonly couple the power supply pads of the plurality ofsemiconductor chips to an external device; and a signal terminalconfigured to commonly couple the input/output pads of the plurality ofsemiconductor chips to the external device.
 8. A method of detecting afailure in semiconductor chips of a multi-chip package semiconductordevice, the method comprising: commonly providing a power to thesemiconductor chips of the multi-chip package semiconductor devicethrough a power supply terminal; setting one of the semiconductor chipsto a disabled state and the rest of the semiconductor chips to anenabled state based on a test mode set signal; measuring a currentflowing through the power supply terminal commonly coupled to thesemiconductor chips; and determining a failure of the disabledsemiconductor chip by comparing the measured current and a normalcurrent corresponding to a normal operation state.
 9. The method ofclaim 8, wherein setting one of the semiconductor chips to a disabledstate includes preventing a power voltage from being provided to aninternal function block of the disabled semiconductor chip; and allowingthe power voltage to be provided to the internal function block of theenabled semiconductor chips.
 10. The method of claim 8, wherein thesemiconductor chips are sequentially set to a disabled state, andmeasuring the current flowing through the power supply terminal anddetermining the failure of the individually disabled semiconductor chipare repeated for each disabled semiconductor chip.